MAX5890EGK+D【PDF 15/16 页】IC DAC 14BIT LVDS 600MSPS 68-QFN

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Sheet目录2011

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MAX5890

14-Bit, 600Msps, High-Dynamic-Performance

DAC with LVDS Inputs

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PIN

NAME

FUNCTION

1, 3, 5, 46, 48,

50, 52, 54, 56,

58, 60, 63, 65,

D2N, D1N, D0N,

D13N, D12N, D11N,

D10N, D9N, D8N,

D7N, D6N, D5N,

D4N, D3N

Differential Negative LVDS Inputs. Data bits D0–D13 (offset binary format).

2, 4, 45, 47,

49, 51, 53, 55,

57, 59, 62, 64,

66, 68

D1P, D0P, D13P,

D12P, D11P, D10P,

D9P, D8P, D7P, D6P,

D5P, D4P, D3P, D2P

Differential Positive LVDS Inputs. Data bits D0–D13 (offset binary format).

6–9

N.C.

No Connection. Leave floating or connect to DGND.

DGND

Digital Ground. Ground return for DVDD3.3 and DVDD1.8.

DVDD3.3

Digital Supply Voltage. Accepts a 3.135V to 3.465V supply voltage range. Bypass with a

0.1F capacitor to DGND.

Power-Down Input. Set PD high to force the DAC into power-down mode. Set PD low for

normal operation. PD has an internal 2A pulldown.

13, 42, 43, 44

N.C.

No Connection. Leave floating or connect to AGND.

14, 21, 22, 25,

26, 31, 32

AVDD3.3

Analog Supply Voltage. Accepts a 3.135V to 3.465V supply voltage range. Bypass with a

0.1F capacitor to AGND.

15, 20, 23, 24,

27, 30, 33

AGND

Analog Ground. Ground return for AVDD3.3 and AVDD1.8.

REFIO

Reference I/O. Output of the internal 1.2V precision bandgap reference. Bypass with a

0.1F capacitor to AGND. REFIO can be driven with an external reference source.

FSADJ

Full-Scale Current Adjustment. Connect an external resistor RSET between FSADJ and

DACREF to set the output full-scale current. The output full-scale current is equal to 32 x

VREF / RSET.

DACREF

Current-Set Resistor Return Path. Internally connected to ground, but do not use as

ground connection.

19, 34, 35

AVDD1.8

Analog Supply Voltage. Accepts a 1.71V to 1.89V supply voltage range. Bypass with a

0.1F capacitor to AGND.

OUTN

Complementary DAC Output. Negative terminal for current output.

OUTP

DAC Output. Positive terminal for current output.

36, 41

AVCLK

Clock Supply Voltage. Accepts a 3.135V to 3.465V supply voltage range. Bypass with a

0.1F capacitor to CGND.

37, 40

CGND

Clock Supply Ground

CLKN

Complementary Converter Clock Input. Negative input terminal for differential converter

clock.

CLKP

Converter Clock Input. Positive input terminal for differential converter clock.

DVDD1.8

Digital Supply Voltage. Accepts a 1.71V to 1.89V supply voltage range. Bypass with a

0.1F capacitor to DGND.

—EP

Exposed Pad. Must be connected to common point for AGND, DGND, and CGND through

a low-impedance path. EP is internally connected to AGND, DGND, and CGND.

Pin Description

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